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VHDL

PostPosted: 10 Mar 2015, 10:09
by christian007
Salve
ho bosogo di aiuto per correggere alcuni errori sul questo codice
grazie mille.

Code: Select all
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


Package package_adder_multi is
   
   function adder(a,b: in std_logic_vector ;cin:in std_logic) return std_logic_vector;
   function multi(a,b: in std_logic_vector ;cin:in std_logic) return std_logic_vector;
   
    
end  package_adder_multi;

package body package_adder_multi is   
      
   
   function adder (a,b :in std_logic_vector;cin :in std_logic ) return std_logic_vector  is
   variable sum:std_logic_vector(3 downto 0);
     variable resto:std_logic;
     variable state:bit_vector(2 downto 0);
        generic (tr:time :=9 ns)
       begin
      
     P1:process
     begin
        c2:case state is
         when "000" => sum<='0'after tr;
         resto<='0' after tr;
         when "010"  => sum<='1'after tr;
         resto<='0'after tr ;
         when  "001" =>  sum<='1'after tr;
         resto<='0'after tr ;
         when  "100" => sum<='1'after tr;
         resto<='0'after tr ;
         when   "111" => sum<='1'after tr;
         resto<='1' after tr;
         when "110 " => sum<='0' after tr;
         resto<='1' after tr;   
         when "011" => sum<='0' after tr;
         resto<='1' after tr;   
         when " 101" => sum<='0' after tr;
         resto<='1' after tr;   
         when "11x " => sum<='x' after tr ;
         resto<='1' after tr ;
         when " x11 " => sum<='x' after tr ;
         resto<='1' after tr ;
         when " 1x1" => sum<='x' after tr ;
         resto<='1' after tr ;
         when others => sum<='x'after tr ;
         resto<='x' after tr ; 
         and case  c2;

return sum;

end process;


end function adder;
      function multi1 (a,b :in std_logic_vector;cin :in std_logic ) return std_logic_vector is 
      variable multi:std_logic_vector(3 downto 0);
      variable resto1:std_logic;
      
     variable state:std_logic;
    
     begin
       
      generic (tr:time :=9 ns);
         
      begin
         if(a='0' or b='0'or cin='0')then
            multi<='0' after tr;
            resto1<='0' after tr ;
             elsif(a='1' and b='1' and cin='1')then
            multi<='1' after tr ;
            resto1<='0' after tr;
            elsif others('x')after tr ;
         end if ;   
   return multi;
end function  multi1;
         
end  package_adder_multi;