Bit 7 of Register 0 is the clock halt (CH) bit. When this bit is set to 1, the
oscillator is disabled. When cleared to 0, the oscillator is enabled.
#define fosc 4000000 ; 4MHz
;Put TWI equate lines in main code and adjust as needed
;
;TWI equates
;
#define TWI_scl_bitrate_l 100000 ;Desired TWI low speed bit rate
#define TWI_scl_bitrate_h 400000 ;Desired TWI high speed bit rate
#define TWI_TWPS 0x00 ;TWI prescaler
#define TWI_TWBR_L (fosc/TWI_scl_bitrate_l-16)/2 ;Works out TWBR low speed value
#define TWI_TWBR_H (fosc/TWI_scl_bitrate_h-16)/2 ;Works out TWBR high speed value
;Initialise TWI in low speed mode
TWI_Master_Init_low:
ldi temp1,TWI_TWBR_L ;Set bit rate register for low speed
rjmp TWI_Init
;Initialise TWI in high speed mode
TWI_Master_Init_high:
ldi temp1,TWI_TWBR_H ;Set bit rate register for high speed
;Initialize TWI as master
TWI_Init:
sts TWBR,temp1
ldi temp1,TWI_TWPS ;Set prescaler register
sts TWSR,temp1
ldi temp1,(1<<TWINT)|(1<<TWSTO)|(1<<TWEN) ; Enable TWI
sts TWCR,temp1
ret
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