# Reading C:/altera/13.0sp1/modelsim_ase/tcl/vsim/pref.tcl 
# do accumulatore_run_msim_rtl_vhdl.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Modifying C:\altera\13.0sp1\modelsim_ase\win32aloem/modelsim.ini
# 
# vcom -93 -work work {C:/Users/giuseppe/Desktop/quartus/accumulatore/Reg_9.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity Reg_9
# -- Compiling architecture Reg_9 of Reg_9
# vcom -93 -work work {C:/Users/giuseppe/Desktop/quartus/accumulatore/accumulatore.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity accumulatore
# -- Compiling architecture accumulatore of accumulatore
# vcom -93 -work work {C:/Users/giuseppe/Desktop/quartus/accumulatore/xor_my.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity xor_my
# -- Compiling architecture xor_my of xor_my
# vcom -93 -work work {C:/Users/giuseppe/Desktop/quartus/accumulatore/or_my.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity or_my
# -- Compiling architecture or_my of or_my
# vcom -93 -work work {C:/Users/giuseppe/Desktop/quartus/accumulatore/Nfull_adder.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity Nfull_adder
# -- Compiling architecture Nfull_adder of Nfull_adder
# vcom -93 -work work {C:/Users/giuseppe/Desktop/quartus/accumulatore/half_adder.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity half_adder
# -- Compiling architecture half_adder of half_adder
# vcom -93 -work work {C:/Users/giuseppe/Desktop/quartus/accumulatore/full_adder.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity full_adder_new
# -- Compiling architecture full_adder_new of full_adder_new
# vcom -93 -work work {C:/Users/giuseppe/Desktop/quartus/accumulatore/and_my.vhd}
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity and_my
# -- Compiling architecture and_my of and_my
# 
vsim -voptargs=+acc rtl_work.accumulatore
# vsim -voptargs=+acc rtl_work.accumulatore 
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading rtl_work.accumulatore(accumulatore)
# Loading rtl_work.nfull_adder(nfull_adder)
# Loading rtl_work.full_adder_new(full_adder_new)
# Loading rtl_work.half_adder(half_adder)
# Loading rtl_work.xor_my(xor_my)
# Loading rtl_work.and_my(and_my)
# Loading rtl_work.or_my(or_my)
# Loading rtl_work.reg_9(reg_9)
add wave -position insertpoint  \
sim:/accumulatore/a
add wave -position insertpoint  \
sim:/accumulatore/c_in
add wave -position insertpoint  \
sim:/accumulatore/clka
add wave -position insertpoint  \
sim:/accumulatore/resa
add wave -position insertpoint  \
sim:/accumulatore/ena
add wave -position insertpoint  \
sim:/accumulatore/cout
add wave -position insertpoint  \
sim:/accumulatore/sout
add wave -position insertpoint  \
sim:/accumulatore/aux0
add wave -position insertpoint  \
sim:/accumulatore/aux4
add wave -position insertpoint  \
sim:/accumulatore/aux1
add wave -position insertpoint  \
sim:/accumulatore/aux2
add wave -position insertpoint  \
sim:/accumulatore/aux3
force -freeze sim:/accumulatore/a 00000010 0
force -freeze sim:/accumulatore/c_in 0 0
force -freeze sim:/accumulatore/clka 1 0, 0 {5 ps} -r 10
force -freeze sim:/accumulatore/resa 0 0
force -freeze sim:/accumulatore/ena 1 0
run
run
add wave -position insertpoint  \
sim:/accumulatore/blocco2/q
run
run
add wave -position insertpoint  \
sim:/accumulatore/blocco2/d
run
